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Re: thread-ready ABIs

To: "H . J . Lu" <hjl@lucon.org>
Subject: Re: thread-ready ABIs
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Mon, 21 Jan 2002 14:43:51 +0100 (MET)
Cc: "Kevin D. Kissell" <kevink@mips.com>, Machida Hiroyuki <machida@sm.sony.co.jp>, drepper@redhat.com, GNU C Library <libc-alpha@sources.redhat.com>, linux-mips@oss.sgi.com
In-reply-to: <20020120111912.A6918@lucon.org>
Organization: Technical University of Gdansk
Reply-to: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Sender: owner-linux-mips@oss.sgi.com
On Sun, 20 Jan 2002, H . J . Lu wrote:

> As I understand, we don't need k1 based semaphore for MIPS II or above.
> So many processors can still benefit from the thread register. We can
> use a system call to implement loading a thread register. So it is
> a trade off between system-call/k1 for thread-register/semaphore. We
> can make it a configure time option. Since PS2 is already using k1 for
> semaphore, I'd like to see it get merged in ASAP so that anything we
> do won't break PS2.

 I believe we need not trade anything off if we split k1 into two parts. 
We could use e.g. the 31 MSBs for the thread register and the LSB for the
ll/sc equivalent.  Other splits are possible if the ll/sc emulation needs
more bits. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +



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