linux-mips
[Top] [All Lists]

Re: thread-ready ABIs

To: "H . J . Lu" <hjl@lucon.org>
Subject: Re: thread-ready ABIs
From: Dominic Sweetman <dom@algor.co.uk>
Date: Sat, 19 Jan 2002 12:27:52 +0000
Cc: "Kevin D. Kissell" <kevink@mips.com>, Ulrich Drepper <drepper@redhat.com>, GNU libc hacker <libc-hacker@sources.redhat.com>, linux-mips@oss.sgi.com
In-reply-to: <20020118201139.A847@lucon.org>
References: <m3elkoa5dw.fsf@myware.mynet> <20020118101908.C23887@lucon.org> <01b801c1a081$3f6518e0$0deca8c0@Ulysses> <20020118201139.A847@lucon.org>
Sender: owner-linux-mips@oss.sgi.com
User-agent: SEMI/1.13.7 (Awazu) CLIME/1.13.6 (中ノ庄) MULE XEmacs/21.1 (patch 14) (Cuyahoga Valley) (i386-redhat-linux)
H . J . Lu (hjl@lucon.org) writes:

> > It would, in principle, be possible to save/restore k0
> > or k1 (but not both) if no other clever solution can be found.  
> > There are other VM OSes that manage to do so for MIPS, 
> > for other outside-the-old-ABI reasons.  It does, of course,
> > add some instructions and some memory traffic to the 
> > low-level exception handling , and we would have to look 
> > at whether we would want to make such a feature standard 
> > or specific to a "thread-ready" kernel build.
> 
> I like the read-only k0 idea. We just need to make a system call to
> tell kernel what value to put in k0 before returning to the user space.
> It shouldn't be too hard to implement. I will try it next week.

You could, I guess, wire a TLB entry to map the thread register into
the highest virtual memory region of the machine (the top of 'kseg2'),
which is accessible in a single instruction as a negative offset from
$0.  The kernel can write it through kseg0 or 64-bit equivalent, if
you're a bit careful about cache aliases.

Reading something out of the cache is pretty cheap: would that be
close enough to a 'register' to do the job?  There's no change to
critical routines, that way.

Dominic Sweetman
Algorithmics Ltd.

<Prev in Thread] Current Thread [Next in Thread>