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Re: thread-ready ABIs

To: Ulrich Drepper <drepper@redhat.com>
Subject: Re: thread-ready ABIs
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 18 Jan 2002 23:17:14 +0100 (MET)
Cc: "H . J . Lu" <hjl@lucon.org>, linux-mips@oss.sgi.com
In-reply-to: <m3zo3b1ghf.fsf@myware.mynet>
Organization: Technical University of Gdansk
Sender: owner-linux-mips@oss.sgi.com
On 18 Jan 2002, Ulrich Drepper wrote:

> > Where did you get extraneous registers for the i386
> > from (especially given the usual register shortage there)?
> 
> %gs

 Ah well, then you just have it by an accident and not because it was
specifically designed to be spare...

> > Maybe we could use the same approach for MIPS.
> 
> I doubt it.

 Indeed.

> > Where to look for the code in glibc in a current snapshot?
> 
> %gs is used for a long time linuxthreads/sysdeps/386/useldt.h

 Thanks.

> >  One possible approach is to reserve GOT entries for thread registers. 
> > While not as fast as CPU's registers, if frequently accessed they would
> > stick in the cache.  Since the ABI mandates the code to keep a pointer to
> > the GOT in the gp register, accesses to got entries need only a single
> > instruction.  I haven't thought on it much -- someone might have a better
> > idea. 
> 
> How would you have different values for different threads?  It would
> mean having multiple GOTs which is a resource waste and a nightmare in
> resource management.

 OK, now I understand you need some kind of a tid, that needs not be
writeable.  A read-only register can be moderately easily provided by
either k0 or k1 if exit paths of exceptions reload the given one.  The
trail code of exceptions only needs one of them at most. 

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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