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Re: thread-ready ABIs

To: Justin Carlson <justincarlson@cmu.edu>
Subject: Re: thread-ready ABIs
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 18 Jan 2002 22:42:15 +0100 (MET)
Cc: drepper@redhat.com, linux-mips@oss.sgi.com
In-reply-to: <1011389085.7765.69.camel@gs256.sp.cs.cmu.edu>
Organization: Technical University of Gdansk
Sender: owner-linux-mips@oss.sgi.com
On 18 Jan 2002, Justin Carlson wrote:

> We could, theoretically, free up k1 or k0 (but not both) at the expense
> of some time in the stackframe setup at the userland/kernel boundary and
> some time in the fast TLB handler.  This wouldn't be read-only from
> userland, though, but is that really a hard requirement?  

 Much, *much* time, especially in the case of TLB exceptions.

> There is precedent for hijacking some CP0 registers for purposes other
> than originally intended, e.g., the WATCH registers for holding the
> kernel stack pointer.  I don't have a mips spec in front of me, though,

 That's not used exactly a stack pointer, but as a safeguard.  I'm still
thinking on a better use of this register, i.e. as a watchpoint for gdb. 

> so I don't know if any CP0 registers are readable from userland: I seem
> to remember that all mfc0 ops are priveleged at the instruction level,
> not the register level, though.

 Technically you can make cp0 registers r/w accessible from the userland,
but that's unacceptable for us.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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