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Re: thread-ready ABIs

To: "H . J . Lu" <hjl@lucon.org>
Subject: Re: thread-ready ABIs
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 18 Jan 2002 21:03:38 +0100 (MET)
Cc: Ulrich Drepper <drepper@redhat.com>, GNU libc hacker <libc-hacker@sources.redhat.com>, linux-mips@oss.sgi.com
In-reply-to: <20020118101908.C23887@lucon.org>
Organization: Technical University of Gdansk
Reply-to: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Sender: owner-linux-mips@oss.sgi.com
On Fri, 18 Jan 2002, H . J . Lu wrote:

> > This means that unless all architectures get thread registers (or
> > equivalent things like Alpha's special code) we'll have a two class
> > society of platforms where all code written for the platforms without
> > thread register can be run on the other systems, but not vice versa.
[...]
> On the other hand, can we change the mips kernel to save k0 or k1 for
> user space?

 No way.  MIPS doesn't predefine any stack-switching hardware and it
doesn't save any registers on exceptions (except from copying pc to cp0's
epc or errorepc).  The k0, k1 registers are defined as reserved for the
kernel use to switch to a kernel stack and save current values of other
registers upon a kernel entry due to an exception.  The general exception
handler (used for almost everything, including interrupts for most
systems) uses the registers this way to "bootstrap" itself.

 The dedicated TLB exception handler, which needs to be very fast for any
reasonable performance to achieve, uses these two registers solely,
without even touching anything else.

 As a result, anything written to k0 or k1 is lost immediately after the
first exception to happen afterwards. 

 Of course, this use of k0, k1 is purely conventional -- they are ordinary
32-bit general-purpose registers from the hardware point of view.  Only
zero and, to some extent, ra registers are different on MIPS. 

 The usage of all 32 registers is fixed in the ABI for MIPS.  But what
about that Alpha's special code?  It could possibly be reused given the
large Alpha's similarity to MIPS. 

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +



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