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RE: MIPS64 status?

To: Matthew Dharm <mdharm@momenco.com>
Subject: RE: MIPS64 status?
From: Jason Gunthorpe <jgg@debian.org>
Date: Mon, 14 Jan 2002 16:59:44 -0700 (MST)
Cc: linux-mips@oss.sgi.com
In-reply-to: <NEBBLJGMNKKEEMNLHGAICENCCEAA.mdharm@momenco.com>
Sender: owner-linux-mips@oss.sgi.com
On Mon, 14 Jan 2002, Matthew Dharm wrote:

> Does this mean we could map PCI memory/IO addresses above 4G and have
> it work?

Ooh, don't go there :> We looked at that and actually did it then backed
it out.

The PCI spec (particuarly PCI-X) tries to make it possible, but in a
general system with PCI sockets/etc it is just is not feasible. PCI
bridges need to be located below 4G, as do the majority of devices made. 
There is also a performance hit for having device registers > 4G.

You'd definately need the mips64 kernel to do that, or use ugly wired TLB
entries with normal mips.

Jason


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