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Re: [PATCH] disable interrupt for non-LLSC atomic set

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: [PATCH] disable interrupt for non-LLSC atomic set
From: Jun Sun <jsun@mvista.com>
Date: Fri, 11 Jan 2002 09:23:46 -0800
Cc: ralf@oss.sgi.com, linux-mips@oss.sgi.com
In-reply-to: <Pine.GSO.3.96.1020111115109.11015A-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Fri, Jan 11, 2002 at 11:54:24AM +0100
References: <3C3E458A.B2AEC3CA@mvista.com> <Pine.GSO.3.96.1020111115109.11015A-100000@delta.ds2.pg.gda.pl>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5i
On Fri, Jan 11, 2002 at 11:54:24AM +0100, Maciej W. Rozycki wrote:
> On Thu, 10 Jan 2002, Jun Sun wrote:
> 
> > The current MIPS_ATOMIC set code for no-LLSC case does a load and store with
> > interrupt open.  This is potentially dangerous as an interrupt could happen
> > in-between and cause the value changed inside the interrupt handler. 
> 
>  No need to -- no sane interrupt handler will ever access a user's atomic
> variable. 
>

OK, I have to reveal the secret desire :-).  I have a patch
that makes MIPS kernel preemptible, and that unprotected operation
becomes very volunerable with the preemptible patch.

Jun

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