| To: | Carsten Langgaard <carstenl@mips.com> |
|---|---|
| Subject: | Re: Toshiba TX3927 board boot problem. |
| From: | Ralf Baechle <ralf@oss.sgi.com> |
| Date: | Tue, 30 Oct 2001 15:13:08 +0100 |
| Cc: | Alice Hennessy <ahennessy@mvista.com>, Atsushi Nemoto <nemoto@toshiba-tops.co.jp>, ajob4me@21cn.com, linux-mips@oss.sgi.com |
| In-reply-to: | <3BDE6671.7776CB4B@mips.com>; from carstenl@mips.com on Tue, Oct 30, 2001 at 09:36:01AM +0100 |
| References: | <20011026095319.1C4BBB474@topsms.toshiba-tops.co.jp> <20011026.225806.63990588.nemoto@toshiba-tops.co.jp> <20011029.160225.59648095.nemoto@toshiba-tops.co.jp> <3BDD140E.432D795B@mips.com> <3BDDF193.B6405A7F@mvista.com> <20011030013223.B6614@dea.linux-mips.net> <3BDE0FAF.1E3556A9@mvista.com> <3BDE6671.7776CB4B@mips.com> |
| Sender: | owner-linux-mips@oss.sgi.com |
| User-agent: | Mutt/1.2.5i |
On Tue, Oct 30, 2001 at 09:36:01AM +0100, Carsten Langgaard wrote: > > So, we should not set CU1 generically for FPU-less CPUs especially since a > > known problem exists > > for the tx3927? Ie, qualify all setting of CU1 as follows: > > > > if (mips_cpu.options & MIPS_CPU_FPU) > > set_cp0_status(ST0_CU1); > > And while we are at it, could we handle the CP0 hazard of 4 nops, between > setting the CU1 bit in the status register and executing > the first floating point instruction, on CPU which got a FPU. Which CPUs actually need four nops? Just working on a patch; I found a bunch more place where we were playing with the CU1 bit. Ralf |
| Previous by Date: | Re: [LV] FYI: Mopd ELF support, Dave Airlie |
|---|---|
| Next by Date: | Re: Toshiba TX3927 board boot problem., Carsten Langgaard |
| Previous by Thread: | Re: Toshiba TX3927 board boot problem., Carsten Langgaard |
| Next by Thread: | Re: Toshiba TX3927 board boot problem., Carsten Langgaard |
| Indexes: | [Date] [Thread] [Top] [All Lists] |