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Re: Malta probs

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: Malta probs
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Wed, 24 Oct 2001 18:56:44 +0200
Cc: Petko Manolov <pmanolov@lnxw.com>, linux-mips@oss.sgi.com
In-reply-to: <004501c15cab$88055b60$0deca8c0@Ulysses>; from kevink@mips.com on Wed, Oct 24, 2001 at 06:47:10PM +0200
References: <200110230102.f9N12kb20443@oss.sgi.com> <3BD5D236.8D0CE33C@lnxw.com> <20011023224718.A6283@dea.linux-mips.net> <004501c15cab$88055b60$0deca8c0@Ulysses>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5i
On Wed, Oct 24, 2001 at 06:47:10PM +0200, Kevin D. Kissell wrote:

> A clue - a machine check exception results
> when there are two identical values in the
> TLB, which is unhealthy for associative RAM
> arrays (never mind that synthesized MIPS
> 4K and 5K cores may or may not actually
> have associative RAM for the TLB).  In the
> 4K cores, this condition results even if the
> two identical values are non-Valid, which was
> not true in the R4000 and R5000 CPUs, and
> which necessitated a tweak to the TLB flush
> and invaldate routines to ensure that each entry
> is written with a unique invalid value (a function
> of the index).
> 
> Please double-check that the TLB flush
> code that you are using does this.

I fixed this problem already last night.

  Ralf

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