Re: Malta probs

[Ralf Baechle <ralf@oss.sgi.com>]

On Wed, Oct 24, 2001 at 06:47:10PM +0200, Kevin D. Kissell wrote:

> A clue - a machine check exception results
> when there are two identical values in the
> TLB, which is unhealthy for associative RAM
> arrays (never mind that synthesized MIPS
> 4K and 5K cores may or may not actually
> have associative RAM for the TLB).  In the
> 4K cores, this condition results even if the
> two identical values are non-Valid, which was
> not true in the R4000 and R5000 CPUs, and
> which necessitated a tweak to the TLB flush
> and invaldate routines to ensure that each entry
> is written with a unique invalid value (a function
> of the index).
> 
> Please double-check that the TLB flush
> code that you are using does this.

I fixed this problem already last night.

  Ralf