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Re: Malta probs

To: ralf@oss.sgi.com
Subject: Re: Malta probs
From: Atsushi Nemoto <nemoto@toshiba-tops.co.jp>
Date: Wed, 24 Oct 2001 22:07:29 +0900 (JST)
Cc: pmanolov@Lnxw.COM, linux-mips@oss.sgi.com
In-reply-to: <20011024024308.A21460@dea.linux-mips.net>
Organization: TOSHIBA Personal Computer System Corporation
References: <20011023224718.A6283@dea.linux-mips.net> <3BD5E193.BB41A907@lnxw.com> <20011024024308.A21460@dea.linux-mips.net>
Sender: owner-linux-mips@oss.sgi.com
>>>>> On Wed, 24 Oct 2001 02:43:08 +0200, Ralf Baechle <ralf@oss.sgi.com> said:
ralf> It wasn't really changed, the whole lump of arch/mips/mm/ was
ralf> just restructured in a way that allows adding of new CPU types
ralf> and - even more important - get the code maintainable again.  As
ralf> it is right now

In current CVS, All handle_xxx exception handler seems to be complied
with ".set mips3".  Here is a patch.  I think this patch solves the
problem reported by Petko.


diff -urP -x CVS -x .cvsignore linux-sgi-cvs/arch/mips/kernel/entry.S 
linux.new/arch/mips/kernel/entry.S
--- linux-sgi-cvs/arch/mips/kernel/entry.S      Mon Oct 22 10:29:56 2001
+++ linux.new/arch/mips/kernel/entry.S  Wed Oct 24 21:55:16 2001
@@ -180,6 +180,7 @@
                END(except_vec3_r4000)
 
                __FINIT
+               .set    mips0
 
 /*
  * Build a default exception handler for the exceptions that don't need
---
Atsushi Nemoto

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