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Re: IDE DMA mode in Big endian for mips

To: Atsushi Nemoto <nemoto@toshiba-tops.co.jp>
Subject: Re: IDE DMA mode in Big endian for mips
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Date: Thu, 18 Oct 2001 14:33:33 +0400
Cc: hli@quicklogic.com, linux-mips@oss.sgi.com
Organization: NIISI RAN
References: <20011017.113842.41627007.nemoto@toshiba-tops.co.jp> <3BCD506F.9683F0E8@niisi.msk.ru> <20011017.204358.39150084.nemoto@toshiba-tops.co.jp> <20011018.111843.41626947.nemoto@toshiba-tops.co.jp>
Sender: owner-linux-mips@oss.sgi.com
Atsushi Nemoto wrote:
> Can anybody explain me a PCI driver's policy of endianness?  

It depens on device and board. Most drivers assume PCI is little-endian,
but rely on outl implementation in byte swapping policy.

> Should we use cpu_to_le32 with outl/writel?  

If you can't instruct hw to perform byte-swapping for PCI IO, you have
to add cpu_to_le32, it's clear. For writel, i.e. PCI MEM the situation
is a bit subtle. The problem is your videocard, that may or may not
support byte swapping. So, in order to suport videocards that aren't
able to swap bytes, you have to setup PCI MEM in big-endian mode.

Look, for example, at the tulip driver, it swaps bytes for DMA and
doesn't do it for register access.

> Should we use cpu_to_le32 to write 32bit data to DMA area?

DMA data is stream of bytes. I would treat a device/board as broken, if
it would need byte swapping for DMA data.

Regards,
Gleb.

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