| To: | raiko@niisi.msk.ru |
|---|---|
| Subject: | Re: IDE DMA mode in Big endian for mips |
| From: | Atsushi Nemoto <nemoto@toshiba-tops.co.jp> |
| Date: | Thu, 18 Oct 2001 11:18:43 +0900 (JST) |
| Cc: | hli@quicklogic.com, linux-mips@oss.sgi.com |
| In-reply-to: | <20011017.204358.39150084.nemoto@toshiba-tops.co.jp> |
| Organization: | TOSHIBA Personal Computer System Corporation |
| References: | <20011017.113842.41627007.nemoto@toshiba-tops.co.jp> <3BCD506F.9683F0E8@niisi.msk.ru> <20011017.204358.39150084.nemoto@toshiba-tops.co.jp> |
| Sender: | owner-linux-mips@oss.sgi.com |
>>>>> On Wed, 17 Oct 2001 20:43:58 +0900 (JST), Atsushi Nemoto >>>>> <nemoto@toshiba-tops.co.jp> said: nemoto> Yes, I depend on hardware swapping on word/dword access. It nemoto> seems many pci drivers depend on this swapping too. Sorry, last sentence might be wrong. I doubt I have been misunderstanding long time... Can anybody explain me a PCI driver's policy of endianness? Should we use cpu_to_le32 with outl/writel? Should we use cpu_to_le32 to write 32bit data to DMA area? Thank you. --- Atsushi Nemoto |
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