| To: | Jakub Jelinek <jakub@redhat.com> |
|---|---|
| Subject: | Re: PATCH: Update sysdeps/mips/fpu/libm-test-ulps |
| From: | Richard Henderson <rth@twiddle.net> |
| Date: | Thu, 4 Oct 2001 10:24:08 -0700 |
| Cc: | Kjeld Borch Egevang <kjelde@mips.com>, "H . J . Lu" <hjl@lucon.org>, GNU C Library <libc-alpha@sourceware.cygnus.com>, linux-mips mailing list <linux-mips@oss.sgi.com> |
| In-reply-to: | <20011001121053.F3251@sunsite.ms.mff.cuni.cz>; from jakub@redhat.com on Mon, Oct 01, 2001 at 12:10:53PM +0200 |
| References: | <20010914111751.A17316@lucon.org> <Pine.LNX.4.30.0110011106360.16270-100000@coplin19.mips.com> <20011001121053.F3251@sunsite.ms.mff.cuni.cz> |
| Sender: | owner-linux-mips@oss.sgi.com |
| User-agent: | Mutt/1.2.5i |
On Mon, Oct 01, 2001 at 12:10:53PM +0200, Jakub Jelinek wrote: > The way soft-fp interprets Quiet NaNs is not just Intel-way, e.g. SPARC, > Alpha work the same way. E.g. on SPARC, signalling NaN is exp=max, > f=.0xxxxxxxxxx...xxx where at least one of the x bits is set, quiet NaN is > exp=max, f=.1xxxxxxxxxx...xxxxxx. > If MIPS has it backwards, Yes indeed. From the Mips32 spec I have handy: Unbiased E f s b1 Value V Typical Single Bit Pattern E_max+1 != 0 x 1 SNaN 16#7fffffff E_max+1 != 0 x 0 QNaN 16#7fbfffff r~ |
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