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RE: Re: 8259 spurious interrupt (IRQ1,IRQ7,IRQ12..)

To: "'Ralf Baechle'" <ralf@oss.sgi.com>
Subject: RE: Re: 8259 spurious interrupt (IRQ1,IRQ7,IRQ12..)
From: Phil Thompson <Phil.Thompson@pace.co.uk>
Date: Thu, 20 Sep 2001 09:45:14 +0100
Cc: "'Zhang Fuxin'" <fxzhang@ict.ac.cn>, linux-mips@oss.sgi.com
Sender: owner-linux-mips@oss.sgi.com
> -----Original Message-----
> From: Ralf Baechle [mailto:ralf@oss.sgi.com]
> Sent: 19 September 2001 17:41
> To: Phil Thompson
> Cc: 'Zhang Fuxin'; linux-mips@oss.sgi.com
> Subject: Re: Re: 8259 spurious interrupt (IRQ1,IRQ7,IRQ12..)
> 
> 
> On Wed, Sep 19, 2001 at 11:27:14AM +0100, Phil Thompson wrote:
> 
> > Make sure you read the section in the P6032 manual "Tips on 
> programming
> > south bridge interrupt controller(s)" - page 31. I don't 
> see how the 8259
> > code that's part of the MIPS tree can ever be used without changes.
> 
> Can you elaborate?  It's actually being used without problems.

The P6032 documentation recommends using Special Mask Mode to disable the
8259's priority logic so that reading the ISR register gives you the set of
pending interrupts. I took that at face value, so you need to program the
mode and need a function to return the set of pending interrupts (although
you could use i8259A_irq_pending() in loop).

Phil

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