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Re: NON FPU cpus (again)

To: Atsushi Nemoto <nemoto@toshiba-tops.co.jp>
Subject: Re: NON FPU cpus (again)
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Thu, 20 Sep 2001 05:16:43 +0200
Cc: linux-mips@oss.sgi.com
In-reply-to: <20010920.121316.74756227.nemoto@toshiba-tops.co.jp>; from nemoto@toshiba-tops.co.jp on Thu, Sep 20, 2001 at 12:13:16PM +0900
References: <20010207144857.B24485@paradigm.rfc822.org> <20010920.121316.74756227.nemoto@toshiba-tops.co.jp>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5i
On Thu, Sep 20, 2001 at 12:13:16PM +0900, Atsushi Nemoto wrote:

> Following codes in exit_thread() and flush_thread() should be executed
> only if (mips_cpu.options & MIPS_CPU_FPU) == 0, shouldn't it?
> 
>               set_cp0_status(ST0_CU1);
>               __asm__ __volatile__("cfc1\t$0,$31");
> 
> BTW, I can not see any point in copying FCR31 to r0.  What is a
> purpose of the cfc1 instruction?

On CPUs with imprecise exceptions a FPU exception might still be pending
and possibly be taken arbitrarily delayed.  The cfc1 instruction serves
as an exception barrier for such exceptions.  At this time TFP is the
only CPU which features imprecise exceptions.

  Ralf

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