linux-mips
[Top] [All Lists]

Re: questions about some bits of STATUS register and exception priority.

To: machael thailer <dony.he@huawei.com>
Subject: Re: questions about some bits of STATUS register and exception priority...
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Tue, 21 Aug 2001 08:53:53 +0200
Cc: linux-mips@oss.sgi.com
In-reply-to: <001901c129e1$5aaaadc0$8021690a@huawei.com>; from dony.he@huawei.com on Tue, Aug 21, 2001 at 09:34:00AM +0800
References: <000701c12529$e1640580$8021690a@huawei.com> <20010815103314.A11966@bacchus.dhis.org> <000b01c1295e$0f2174c0$8021690a@huawei.com> <20010820230755.A11242@dea.linux-mips.net> <001901c129e1$5aaaadc0$8021690a@huawei.com>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5i
On Tue, Aug 21, 2001 at 09:34:00AM +0800, machael thailer wrote:

>     I am confused about CU0 and UM(ERL EXL) bit of STATUS register.
> 
>     The user manual says that " CP0 is always usable when in Kernel mode,
> regardless of the setting of CU0 bit". Does it mean that when in Kernel mode
> , the CU0 bit is always 1 and in User mode, the CU0 bit is 0? If the CU0 is
> 0, can we be sure that it is in User mode?

In the Linux kernel CU0 is used to indicate that we're running on the
kernel stack.

>      If a user program is running in User mode, an interrupt happens at this
> time(or an error occurs), then it will switch to Kernel mode to run the
> interrupt handler(or the error exception handler). We know that the EXL(or
> ERL) bit of Status register will be set to 1 by hardware. What about the UM
> bit of Status? Does it remain unchangeable or change to 1 too? The user
> manual doesn't say anything about it.

The hardware does not change UM (r4k: KSU bits).

> Another question about exception priority:
> In entry.S, some exception handlers enables global interrupt bit(IE) but
> others disables it.

We have to avoid infinite recursion of exceptions; in same cases it's
just paranoia or minor performance issue.

> Also syscall exception handler enables global interrupt bit(IE). Since the
> interrupt priority  is lowest,If an interrupt happens in a syscall exception
> handler, will it pause the syscall exception handler and run the interrupt
> handler? If not, why it enable the IE bit(STI) in the syscall exception
> handler??
> 
> If two interrupts happens at the same time, how can we decide the larger
> priority interrupt and run its ISR?

That's the decission of implementor of the respective board.  No strict
rules here; in general we priorize the timer interrupt highest but that's
no longer mandatory.

  Ralf

<Prev in Thread] Current Thread [Next in Thread>