> > Using mips-linux-gcc from egcs-2.91.66, I don't see exactly this
> > behavior in the test case above. I *do* see that *if* I have -mcpu=4600
> > set *and* I have not otherwise set the ISA level to be MIPS I or
> > MIPS II (-mips1, -mips2), 64-bit instructions will be emitted.
> > But that's to be expected.
> No, it contradict the GCC documentation:
> `-mcpu=CPU TYPE'
> Assume the defaults for the machine type CPU TYPE when scheduling
> instructions. The choices for CPU TYPE are `r2000', `r3000',
> `r3900', `r4000', `r4100', `r4300', `r4400', `r4600', `r4650',
> `r5000', `r6000', `r8000', and `orion'. Additionally, the
> `r2000', `r3000', `r4000', `r5000', and `r6000' can be abbreviated
> as `r2k' (or `r2K'), `r3k', etc. While picking a specific CPU
> TYPE will schedule things appropriately for that particular chip,
> the compiler will not generate any code that does not meet level 1
> of the MIPS ISA (instruction set architecture) without a `-mipsX'
> or `-mabi' switch being used.
In that case, the tools that I've been using are technically
broken. Surprise surprise. Because -mcpu=4600 is
most assuredly setting the ISA level, even if it doesn't
override one explicitly set!
> > To generate 32-bit code for an
> > R4600-like platform, you need to specify both the ISA level
> > (to deal with issues like the above) and the R4600 pipeline
> > (to get the MAD instruction).
> No MAD on R4600. Again it would be in contradiction with above document-
> ation. Mad you get with:
Right. Sorry. I got the 4600 and 4650 confused. I no longer
understand why "4600" and not "4650" is the model for MIPS32.