Re: ATI Victoria on Malta

["Andrew Thornton" <andrew.thornton@insignia.com>]

Geert,

>Using `atydebug' (from tools in CVS module atyfb at
>http://www.sourceforge.net/projects/linux-fbdev/), the PLL debug values
mean:
>
>| tux$ ./atydebug ac ac 24 df f6 04 00 fd 8e 9e 65 05 00 00 00 00
>| PLL rate = 417.901480 MHz (guessed)
>| bad MCLK post divider 5
>| VCLK0 = 414.623821 MHz
>| VCLK1 = 232.713765 MHz
>| VCLK2 = 86.311678 MHz
>| VCLK3 = 165.521763 MHz
>| tux$
>
>Which looks a bit odd. The same for the 512 K SGRAM.
>
>So I guess the Malta firmware hasn't initialized the RAGE XL yet. And atyfb
>requires an initialized chip.

I guess this is not surprising because the Malta firmware isn't a PC BIOS.

Andrew Thornton