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Re: ATI Victoria on Malta

To: "Geert Uytterhoeven" <Geert.Uytterhoeven@sonycom.com>
Subject: Re: ATI Victoria on Malta
From: "Andrew Thornton" <andrew.thornton@insignia.com>
Date: Tue, 24 Jul 2001 16:51:14 +0100
Cc: "James Simmons" <jsimmons@transvirtual.com>, "Linux-MIPS" <linux-mips@oss.sgi.com>
Sender: owner-linux-mips@oss.sgi.com
Geert,

>Using `atydebug' (from tools in CVS module atyfb at
>http://www.sourceforge.net/projects/linux-fbdev/), the PLL debug values
mean:
>
>| tux$ ./atydebug ac ac 24 df f6 04 00 fd 8e 9e 65 05 00 00 00 00
>| PLL rate = 417.901480 MHz (guessed)
>| bad MCLK post divider 5
>| VCLK0 = 414.623821 MHz
>| VCLK1 = 232.713765 MHz
>| VCLK2 = 86.311678 MHz
>| VCLK3 = 165.521763 MHz
>| tux$
>
>Which looks a bit odd. The same for the 512 K SGRAM.
>
>So I guess the Malta firmware hasn't initialized the RAGE XL yet. And atyfb
>requires an initialized chip.

I guess this is not surprising because the Malta firmware isn't a PC BIOS.

Andrew Thornton



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