linux-mips
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Re: sti() does not work.

To: Ralf Baechle <ralf@oss.sgi.com>
Subject: Re: sti() does not work.
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Mon, 16 Jul 2001 14:46:49 +0200 (MET DST)
Cc: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>, linux-mips@oss.sgi.com
In-reply-to: <20010714130448.C6713@bacchus.dhis.org>
Organization: Technical University of Gdansk
Sender: owner-linux-mips@oss.sgi.com
On Sat, 14 Jul 2001, Ralf Baechle wrote:

> Real wild pig hackers on R3000 were writing code which knows that in the
> load delay slot they still have the old register value available.  So you
> can implement var1++; var2++ as:

 That's crazy...

> Of course only safe with interrupts disabled.  So in a sense introducing
> the load interlock broke semantics of MIPS machine code ;-)

 That broke the MIPS' virtue as well, as MIPS stands for "Microprocessor
without Interlocked Pipeline Stages" (actually mfhi/mflo broke that in the
first place, but it was less significant due to the multiplier being a
separate unit). 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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