On Sat, 14 Jul 2001, Ralf Baechle wrote:
> Real wild pig hackers on R3000 were writing code which knows that in the
> load delay slot they still have the old register value available. So you
> can implement var1++; var2++ as:
That's crazy...
> Of course only safe with interrupts disabled. So in a sense introducing
> the load interlock broke semantics of MIPS machine code ;-)
That broke the MIPS' virtue as well, as MIPS stands for "Microprocessor
without Interlocked Pipeline Stages" (actually mfhi/mflo broke that in the
first place, but it was less significant due to the multiplier being a
separate unit).
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
|