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Re: CONFIG_MIPS_UNCACHED

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: CONFIG_MIPS_UNCACHED
From: Jun Sun <jsun@mvista.com>
Date: Sat, 23 Jun 2001 10:49:32 -0700
Cc: linux-mips@oss.sgi.com
References: <3B34BE3B.B72D40F1@mvista.com> <01ee01c0fc08$66e81e80$0deca8c0@Ulysses>
Sender: owner-linux-mips@oss.sgi.com
"Kevin D. Kissell" wrote:
> 
> > I looked at the code and it appears this config may not work properly.
> >
> > My understanding is that if CPU has been running with cache enabled, and,
> > presummably, have many dirty cache entries, and if you suddenly change
> config
> > register to run kernel uncached, you *don't* get all the dirty cache lines
> > flushed into memory.  Therefore, you will be accessing stale data in
> memory.
> >
> > Is this right?  If so, we need a better way to run CPU uncached.
> >
> > In the past, I have been a private patch to do so.  It seems pretty
> difficult
> > to come up a generic, because we want to figure out the CPU type and
> disable
> > cache *before* kernel starts to modify any memory content.
> 
> Since the kernel cache attribute is never initialized before
> ld_mmu_{whatever} is invoked, and since that Config field
> does not have a well-defined reset state on many MIPS
> CPUs, it would appear that we are in effect trusting the
> bootloader to have done something reasonable like
> set kseg0 to be non-cachable or write-through, either
> of which would be safe for the current code. 

I think you just proposed a fix: check current config register when we turn
off cache.  Thanks. :-)

Jun

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