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Re: Linux on LSI EZ4102

To: Quinn Jensen <jensenq@Lineo.COM>
Subject: Re: Linux on LSI EZ4102
From: Ralph Metzler <rjkm@convergence.de>
Date: Wed, 18 Apr 2001 21:02:16 +0200 (CEST)
Cc: linux-mips@oss.sgi.com
In-reply-to: <3ADDBFA2.7030608@Lineo.COM>
References: <15062.17293.403963.722517@valen.metzler> <3ADDBFA2.7030608@Lineo.COM>
Sender: owner-linux-mips@oss.sgi.com
Quinn Jensen writes:
 > Are the caches two-way (or more)?  If so, check
 > to see if the way select bit(s) are contiguous
 > with the offset for indexed cache operations.
 > If there is a hole, you have to flush in two
 > parts, or flush as if the cache was big enough
 > to span the hole.

The i-cache is two-way and the d-cache one-way.
Since I followed the LSI sample code quite closely when implementing
the flush calls I don't think that this is the problem.
(Although I found one bad bug in the LSI code, so maybe ...) 

I first based my port on the Linux version from linux-vr.sourceforge.net
which is a modified 2.4.0test9. Now it seems others have problems with
caching on that kernel with other MIPS architectures too. 
So, I'll better move to one of the 2.4.3-ac kernels first. I saw that
they contain quite a few changes, especially in the cache handling. 

Cheers,
Ralph

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