Are the caches two-way (or more)? If so, check
to see if the way select bit(s) are contiguous
with the offset for indexed cache operations.
If there is a hole, you have to flush in two
parts, or flush as if the cache was big enough
to span the hole.
Quinn
owner-linux-mips@oss.sgi.com wrote:
Hi,
does anybody have experience with the LSI EZ41XX line of MIPS cores
and Linux, especially regarding the cache handling?
They have a R3000-like MMU architecture and most of the MIPS2 command
set but a totally different cache.
Without cache enabled the Linux port I did works fine but with cache
the ethernet driver and the MMU behave badly. I thought I implemented
the flushing routines correctly but it seems I missed something.
If somebody already did work on this architecture please let me know.
Thanks,
Ralph
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