| To: | "Kevin D. Kissell" <kevink@mips.com> |
|---|---|
| Subject: | Re: Multiple processor support? |
| From: | Jun Sun <jsun@mvista.com> |
| Date: | Mon, 26 Mar 2001 11:20:35 -0800 |
| Cc: | carlson@sibyte.com, Matthew Dharm <mdharm@momenco.com>, linux-mips@oss.sgi.com |
| References: | <NEBBLJGMNKKEEMNLHGAIKELLCAAA.mdharm@momenco.com> <01032316143609.00779@plugh.sibyte.com> <01b801c0b3fb$1770b740$0deca8c0@Ulysses> |
| Sender: | owner-linux-mips@oss.sgi.com |
"Kevin D. Kissell" wrote: > > (Software cache coherency) It is possible, > but tricky, and at times unavoidably inefficient to build a > software-coherent SMP system. I have not heard of anyone > doing so with MIPS/Linux. > How would it be possible? Any reference to the previous implementations? I imagine you would need at least some kind of atomic operation (like ll/sc) working reliably (which itself may require cache coherency). Also, any such scheme should not require massive change in the programming. I am very curious.... Jun |
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