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Re: CONFIG_MIPS_UNCACHED

To: Jun Sun <jsun@mvista.com>
Subject: Re: CONFIG_MIPS_UNCACHED
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Wed, 24 Jan 2001 16:31:02 -0800
Cc: Pete Popov <ppopov@mvista.com>, Quinn Jensen <jensenq@Lineo.COM>, linux-mips@oss.sgi.com
In-reply-to: <3A6F36B8.4F10759B@mvista.com>; from jsun@mvista.com on Wed, Jan 24, 2001 at 12:10:32PM -0800
References: <3A6E132B.9000103@Lineo.COM> <3A6E1977.2B18484D@mvista.com> <3A6F36B8.4F10759B@mvista.com>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5i
On Wed, Jan 24, 2001 at 12:10:32PM -0800, Jun Sun wrote:

> It is really surprising to know this.  It sounds like a CPU bug to me.  Can
> some MIPS "gods" clarify if such a behaviour is a bug or allowed?
> 
> BTW, the CPU in EV96100 is QED RM7000, I believe.

If you want to be strictly correct you have to execute the code that
disables caching of KSEG0 in uncached space like KSEG1, then flush the
caches before you can resume execution in KSEG0.  Otherwise you might
end up with dirty d-caches which when flushed will overwrite more
uptodate data in memory.  The window is very small but yet exists if
things are just right.

  Ralf

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