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Re: broken RM7000 in CVS ...

To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Subject: Re: broken RM7000 in CVS ...
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Mon, 15 Jan 2001 06:37:25 -0200
Cc: jsun@mvista.com (Jun Sun), carlson@sibyte.com, linux-mips@oss.sgi.com
In-reply-to: <E14HDwC-0005GH-00@the-village.bc.nu>; from alan@lxorguk.ukuu.org.uk on Fri, Jan 12, 2001 at 11:48:50PM +0000
References: <3A5F68CB.78D693B3@mvista.com> <E14HDwC-0005GH-00@the-village.bc.nu>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5i
On Fri, Jan 12, 2001 at 11:48:50PM +0000, Alan Cox wrote:

> > My understanding is that we don't have a standard way to probe for external
> > cache (L2 or L3).  So this problem is not only for MIPS32 cpus.
> 
> Cache is very arch specific. You don't want to know how you find L2 cache
> on a MacII for example 8)

Actually the Indy's R4600 / R5000 second level caches also call for the use
of LARTs in a while (1) loop ;-)  Read the generic code had to be changed
in order to support in a sane way.

  Ralf

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