On Tue, Jan 09, 2001 at 08:30:05PM +0100, Kevin D. Kissell wrote:
> My point is that an SSNOP should cause a 1 cycle stall on *any* MIPS
> implementation to date, superscalar or not. It's not documented that
> way for the R10000, but if I recall correctly, it works there too. If one
> wants to standardize on a single mechanism, that's the one to use.
> That's all I'm saying.
I agree on that - except that I haven't seen the various various flavours
of nops documented anywhere except in IRIX's <sys/asm.h> ...
> > Also note that the branch is equivalent to three nops. One for the
> > branch instruction itself, the two more for instructions in the pipeline
> > that get killed. On the R4600 / R500 where the hazard is only a single
> > instruction the branch is equivalent to only a single nop. So while
> > unobvious the branch is a rather neat idea.
> Yes, it's cute, but it relies on accidents of implementation to work,
> and could easily fail on other CPUs otherwise compatible with
> the R4000. In principle, such a branch might incur no delay at
> all on an advanced 64-bit processor. By all means, use it for
> the specific cases of the CPUs on which it is known to work,
> but it should not be used in "default" MIPS CP0 handlers.
This behaviour of the R4000 branch is documented in the R4000 manual's
description of the pipeline.