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Re: CVS Update@oss.sgi.com: linux

To: Ralf Baechle <ralf@oss.sgi.com>
Subject: Re: CVS Update@oss.sgi.com: linux
From: Dominic Sweetman <dom@algor.co.uk>
Date: Sun, 19 Nov 2000 15:16:33 GMT
Cc: Harald Koerfgen <Harald.Koerfgen@home.ivm.de>, linux-cvs@oss.sgi.com, linux-mips@oss.sgi.com, linux-mips@fnet.fr
In-reply-to: <20001118182114.A19710@bacchus.dhis.org>
References: <20001118132233Z553804-494+838@oss.sgi.com> <XFMail.001118180639.Harald.Koerfgen@home.ivm.de> <20001118182114.A19710@bacchus.dhis.org>
Sender: owner-linux-mips@oss.sgi.com
Ralf Baechle (ralf@oss.sgi.com) writes:

> > >       New configuration option CONFIG_MIPS_UNCACHED.  Not yet
> > >       selectable due to the manuals documenting ll/sc operation
> > >       as undefined for uncached memory.
> > 
> > Wouldn't it make sense then to disable CONFIG_CPU_HAS_LLSC as well?
> 
> I'm waiting for authoritative answer from silicon guys before I
> deciede.  In the past I ran kernel entirely uncached and they seemed
> to work even though the documentation made me assume the opposite.

ll/sc between CPUs certainly won't work for uncached accesses, since
they rely on the cache coherency protocols.

On a uniprocessor CPU the ll/sc link is typically broken on any
exception.  You'd have to try very hard to design the CPU so that it
would work any differently for cached and uncached accesses.

-- 
Dominic Sweetman
Algorithmics Ltd
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone: +44 1223 706200 / fax: +44 1223 706250 / home: +44 20 7226 0032
http://www.algor.co.uk

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