On Thu, Oct 05, 2000 at 09:32:41PM -0700, Jun Sun wrote:
> > > > > Ralf, before the perfect solution is found, the following patch makes
> > > > > the gcc complain go away. It just use ".set mips3" pragma.
> > Which, as Ralf correctly observes, will generate code that will
> > crash on 32-bit CPUs,
> Why will it crash 32-bit CPUs? On my R5432 CPU, the lwl/lwr sequence
> executes just fine.
That's a 64-bit CPU with a 32-bit bus ...
> Or do you mean it will crash SOME 32-bit CPUs? Do those 32-bit CPUs
> support lwl or lwr? If they don't, they should generate a reserved
> instruction exception. If they do, I don't see any problem.
It will crash all 32-bit CPUs.
> Not entirely. I was thinking if the unaligned load/store instruction
> corrupts the upper 32 bit content on SOME cpus, maybe we do need to cut
> the upper 32bit as a workaround. Well, I hope it is not necessary.
No, it happens on all CPUs. Interrupts only restore the lower 32-bit of
the registers. Partially this happens for the sake of compatibility with
32-bit cpus, partially it's also the because otherwise 8kb kernel stack
wouldn't be sufficient, we'd have to go up to 16kb stacks which again
has potencial influence on the memory managment that can reduce the
reliability of the kernel when low on memory, it increases the overhead.
In short unless a system has serious needs for 64-bit supporting 64-bit
is quite a loss.