Ralf Baechle wrote:
> On Thu, Oct 05, 2000 at 09:32:41PM -0700, Jun Sun wrote:
> > > > > > Ralf, before the perfect solution is found, the following patch
> > > > > > makes
> > > > > > the gcc complain go away. It just use ".set mips3" pragma.
> > >
> > > Which, as Ralf correctly observes, will generate code that will
> > > crash on 32-bit CPUs,
> > Why will it crash 32-bit CPUs? On my R5432 CPU, the lwl/lwr sequence
> > executes just fine.
> That's a 64-bit CPU with a 32-bit bus ...
That is what the manual claims. However I did find something strange.
I run the following code on R5432:
0x8019dc34 <my_get_unaligned+4>: ldl $a2,7($a0)
0x8019dc38 <my_get_unaligned+8>: ldr $a2,0($a0)
0x8019dc3c <my_get_unaligned+12>: srl $a2,$a2,0x10
As Kevin has guessed, it actually runs fine. However, the register
content in $a2 is not right. Basically it appears that $a2 is a 32-bit
register instead of 64-bit register. I put a srl instruction to make
sure I was not fooled by gdb.
I know R5432 is derived from R5000 FOR 32-bit systems. I guess there
are probably a lot of short-cuts for 64-bit operations.