"Kevin D. Kissell" wrote:
> Jun Sun wrote:
> > "Kevin D. Kissell" wrote:
> > >
> > > > > > Ralf, before the perfect solution is found, the following patch
> > > > > > the gcc complain go away. It just use ".set mips3" pragma.
> > >
> > > Which, as Ralf correctly observes, will generate code that will
> > > crash on 32-bit CPUs,
> > Why will it crash 32-bit CPUs? On my R5432 CPU, the lwl/lwr sequence
> > executes just fine.
> > Or do you mean it will crash SOME 32-bit CPUs? Do those 32-bit CPUs
> > support lwl or lwr? If they don't, they should generate a reserved
> > instruction exception. If they do, I don't see any problem.
> Please re-read my previous message. I wasn't talking about the
> MIPS I lwl/lwr sequence for loading an unaligned 32-bit word, I was
> talking about the MIPS III ldl/ldr sequence for loading an unaligned
> 64-bit doubleword.
> Kevin K.
Ahh, my bad.
Although the usb does use get_unaligned(u64) (ldl/ldr), it actually does
not run into it - at least in my test so far. That probably explains
why my fix runs on the R5432 CPU so far.
Ralf, I notice you have fixed it in the CVS tree. Just did a test, and
it looks good here.