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Re: CVS Update@oss.sgi.com: linux

To: Kanoj Sarcar <kanoj@google.engr.sgi.com>
Subject: Re: CVS Update@oss.sgi.com: linux
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Thu, 7 Sep 2000 02:26:52 +0200
Cc: linux-mips@oss.sgi.com
In-reply-to: <200009070005.RAA27824@google.engr.sgi.com>; from kanoj@google.engr.sgi.com on Wed, Sep 06, 2000 at 05:05:18PM -0700
References: <20000907020237.B20605@bacchus.dhis.org> <200009070005.RAA27824@google.engr.sgi.com>
Sender: owner-linux-mips@oss.sgi.com
On Wed, Sep 06, 2000 at 05:05:18PM -0700, Kanoj Sarcar wrote:

> > On Wed, Sep 06, 2000 at 04:51:19PM -0700, Kanoj Sarcar wrote:
> > 
> > > The act of flushing the L2 cache, should include flushing the L1
> > > cache, whether done by software or processor provided primitives, 
> > > to guarantee the inclusion principle.
> > 
> > The inclusion principle is not true for all processor types.
> 
> Which processor is supported out of the mips64 tree that does
> not obey the inclusion principle?

The R4600SC and R5000SC IP22.  RM7000 (patches pending) and probably most
future MIPS CPUs.

  Ralf

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