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Re: CVS Update@oss.sgi.com: linux

To: ralf@oss.sgi.com (Ralf Baechle)
Subject: Re: CVS Update@oss.sgi.com: linux
From: Kanoj Sarcar <kanoj@google.engr.sgi.com>
Date: Wed, 6 Sep 2000 17:05:18 -0700 (PDT)
Cc: linux-mips@oss.sgi.com
In-reply-to: <20000907020237.B20605@bacchus.dhis.org> from "Ralf Baechle" at Sep 07, 2000 02:02:37 AM
Sender: owner-linux-mips@oss.sgi.com
> 
> On Wed, Sep 06, 2000 at 04:51:19PM -0700, Kanoj Sarcar wrote:
> 
> > The act of flushing the L2 cache, should include flushing the L1
> > cache, whether done by software or processor provided primitives, 
> > to guarantee the inclusion principle.
> 
> The inclusion principle is not true for all processor types.

Which processor is supported out of the mips64 tree that does
not obey the inclusion principle?

Kanoj


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