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Re: CVS Update@oss.sgi.com: linux

To: Kanoj Sarcar <kanoj@google.engr.sgi.com>
Subject: Re: CVS Update@oss.sgi.com: linux
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Thu, 7 Sep 2000 02:02:37 +0200
Cc: linux-mips@oss.sgi.com
In-reply-to: <200009062351.QAA14035@google.engr.sgi.com>; from kanoj@google.engr.sgi.com on Wed, Sep 06, 2000 at 04:51:19PM -0700
References: <20000907014521.A20605@bacchus.dhis.org> <200009062351.QAA14035@google.engr.sgi.com>
Sender: owner-linux-mips@oss.sgi.com
On Wed, Sep 06, 2000 at 04:51:19PM -0700, Kanoj Sarcar wrote:

> The act of flushing the L2 cache, should include flushing the L1
> cache, whether done by software or processor provided primitives, 
> to guarantee the inclusion principle.

The inclusion principle is not true for all processor types.

> Notwithstanding, feel free to add in a call to flush_cache_l1()
> (and I don't know whether you want to flush the i and d caches
> both, or just one), making sure there are no compile breakages.
> (the breakage that I fixed was due to the fact that there is no
> __flush_cache_all for mips64).

Sorry, that line leaked in from my private tree.

  Ralf

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