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Re: PROPOSAL : multi-way cache support in Linux/MIPS

To: "Dominic Sweetman" <dom@algor.co.uk>, "Jun Sun" <jsun@mvista.com>
Subject: Re: PROPOSAL : multi-way cache support in Linux/MIPS
From: "Kevin D. Kissell" <kevink@mips.com>
Date: Wed, 2 Aug 2000 20:36:17 +0200
Cc: <linux@cthulhu.engr.sgi.com>, <linux-mips@fnet.fr>, <ralf@oss.sgi.com>
Sender: owner-linux-mips@oss.sgi.com
Dom Sweetman writes:
>So far as I know the Vr5432 is the only CPU to do anything so silly as
>using the lowest index bits to select the "way". 

Alas, the R10000 does the same silly thing, and while you
and I might not consider such a venerable processor interesting
for new embedded MIPS/Linux designs, our friends who
are trying to replace IRIX with Linux on their SGI boxes
are going to have to deal with them for a little while longer.

>The MS-selects-way organisation permits the cache to be initialised
>without the software ever needing to know how many ways it has (just
>crank the index up, but being careful about the tendency to recycle
>the same way when pre-filling cache data).

Which is why MIPS belatedly documented it as the "correct"
way to design a multiway cache...

>Cache maintenance should always use "hit" type instructions, and you
>don't need to know the cache organisation for those, even with the
>Vr5432.

The counterargument to *always* using "hit" ops is that they
generate TLB traffic and TLB refills, which some people
find annoying to allow for and in any case time consuming.


            Regards,

            Kevin K.



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