I've cleaned some of the r4xx0.c cache functions yesterday. Aside of shaving
off almost 50% of lat_mmap benchmark results we now also properly assymetric
cache line sizes as seen on the R4300 or used by certain configurations of
the M700 and Mips Magnum.
One of the next things I'll kill is support for split data and instruction
second level caches on R4000 and R4400; I haven't ever heared of such a
configuration actually being used in practice and anyway, it's a runtime
configurable feature so we could get rid of it if we ever run into it.