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More oddities in traps.c

To: "Linux SGI" <linux@cthulhu.engr.sgi.com>
Subject: More oddities in traps.c
From: "Kevin D. Kissell" <kevink@mips.com>
Date: Fri, 21 Apr 2000 10:39:51 +0200
Cc: "Linux/MIPS fnet" <linux-mips@fnet.fr>
Sender: owner-linuxmips@oss.sgi.com
So while we're on the topic of cruft in arch/mips/kernel/traps.c,
does anyone know why the cache error exception vector is
overwritten with a copy of the TLB miss handler as part of
vector setup on R4xxx and R5xxx CPUs?
__

Kevin D. Kissell
MIPS Technologies European Architecture Lab
kevink@mips.com
Tel. +33.4.78.38.70.67
FAX. +33.4.78.38.70.68


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