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Re: Indy crashes

To: Ralf Baechle <ralf@oss.sgi.com>
Subject: Re: Indy crashes
From: "William J. Earl" <wje@cthulhu.engr.sgi.com>
Date: Tue, 15 Feb 2000 17:46:06 -0800 (PST)
Cc: "Kevin D. Kissell" <kevink@mips.com>, Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>, linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr, linux-mips@vger.rutgers.edu
In-reply-to: <20000216022334.A1070@uni-koblenz.de>
References: <006501bf7803$59855ad0$0ceca8c0@satanas.mips.com> <20000216011337.C4633@uni-koblenz.de> <14505.64125.564813.333784@liveoak.engr.sgi.com> <20000216022334.A1070@uni-koblenz.de>
Sender: owner-linuxmips@oss.sgi.com
Ralf Baechle writes:
 > On Tue, Feb 15, 2000 at 05:16:45PM -0800, William J. Earl wrote:
...
 > >       There is a need for a workaround on the R5000 for a "bad $badvaddr" 
 > > problem.  The except_vec0_r45k_bvahwbug() variation does not appear to be
 > > enabled for the R5000.  (It should not be needed for the RM7000 or the 
 > > RM5271.)
 > 
 > I don't have this bug in my erratas documented, can you elaborate on it?

     Sometimes you get a utlbmiss exception when there is already matching
TLB entry.  If you then blindly drop in the TLB entry, you get a duplicate,
which leads to Bad Things (tm).  The workaround is to probe for a duplicate,
and skip the tlbwr if an entry already exists.  It should be enabled on any
real R5000.  

    This is from the R5000 Errata list of 30 October 1997:

----------------------------------------------------------------------
3.  An erroneous JTLB miss exception will be taken under
    these conditions. 

    a) An instruction which does not cause an exception or
       stall is 8 bytes away from the end of a page.
    b) A load or store instruction is the last instruction of that page.
    c) The load/store target address has a matching but invalid
       JTLB entry
    d) The next sequential page is not mapped in the JTLB

    In this situation, when the load/store instruction is executed,
    a JTLB invalid exception should be taken, instead a JTLB miss
    exception is incorrectly taken. If the exception handler
    does a random TLB write to resolve the exception, this will in 
    general insert a duplicate TLB entry for each erroneous exception.
    If the first instruction is a jump or branch, this will cause
    an infinite loop of JTLB miss exceptions to occur upon the return
    from the exception handler.  Otherwise, there will be only one
    erroneous exception, followed by a correct exception, leaving
    one duplicate entry in the TLB.

    A software fix is for the JTLB miss handler to detect this situation,
    by probing for a matching TLB entry (treating a hit as being this case),
    ignore the JTLB miss and treat the exception as an JTLB invalid exception.

    Errata 3 is fixed in Rev 2.0.
----------------------------------------------------------------------

      It is not clear to me that Errata 3 is fixed in all cases in Rev 2.*,
so IRIX has the workaround enabled for all R5000 revisions.

     In Linux, just use except_vec0_r45k_bvahwbug() for any R5000.

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