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Question concerning cache coherency

To: sgi-mips <linux@cthulhu.engr.sgi.com>
Subject: Question concerning cache coherency
From: Jeff Harrell <jharrell@ti.com>
Date: Wed, 19 Jan 2000 10:00:11 -0700
Cc: Ralf Baechle <ralf@oss.sgi.com>, bbrown <bbrown@ti.com>, vwells <vwells@ti.com>, kmcdonald <kmcdonald@ti.com>, mhassler <mhassler@ti.com>
Sender: owner-linuxmips@oss.sgi.com
I have an interesting issue that I would like to run past the MIPS/Linux
newsgroup.  I am
currently porting the MIPS/Linux code to a development board that has a
IDT64475 MIPS
core (64-bit R4xxx core).  I notice that this part does not have any
method of maintaining
cache coherency (i.e., no hardware support for cache coherency).  It is
highly likely that we
will be plugging in a network card on a PCI bus that would be DMA'ing to
a shared memory
space in SDRAM.  I assume that the problem of cache coherency is fixed
by mapping the shared
memory as uncached.  I have not dug into the network drivers (or the
kernel) enough to know whether
this is how the problem is addressed on typical MIPS architectures.  I
guess I have two questions
related to this issue;  Do devices that DMA, typically access uncached
memory  and if so, is a second buffer
required to copy from kernel to user space?  The second question is
concerning the performance hit in
running out of uncached memory,  Have people seen significant
performance degradation when
using uncached memory.  Any insight that anybody can provide would be
greatly appreciated.

Thanks,
Jeff


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jeff Harrell                    Work:  (801) 619-6104
Broadband Access group/TI
jharrell@ti.com
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