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Re: Kernel Semaphores

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: Kernel Semaphores
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Mon, 6 Dec 1999 17:08:32 -0200
Cc: Linux SGI <linux@cthulhu.engr.sgi.com>
In-reply-to: <00b901bf4003$3f583c50$0ceca8c0@satanas.mips.com>
References: <00b901bf4003$3f583c50$0ceca8c0@satanas.mips.com>
Sender: owner-linuxmips@oss.sgi.com
On Mon, Dec 06, 1999 at 05:02:06PM +0100, Kevin D. Kissell wrote:

> Some time ago, I fixed the assembler macros
> for waking_non_zero_interruptable and down_trylock
> to be correct(ish) for MIPSEL and MIPSEB, but
> there remained the issue of their requiring the use
> of 64-bit instructions to work - they "cheat" by using
> the same ll/sc pair to update both the count and the
> waking field of the semaphore.

Btw, we have two variants for all the semaphore code as you know.  We
can eleminate the little endian variant by just swapping the order of
the two atomic_t members in struct semaphore which will eleminate the
maintenance problems.

> To make it work on 32-bit CPUs, I looked at using
> the x386 model, but that one uses interrupt disables
> and is intrinsically SMP-unsafe.

semaphore-helper.h uses spin_lock_irqsave which is smp-safe.  The way
we do things for 64-bit MIPS is just more performant.

  Ralf

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