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Re: EXT2 fs error

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: EXT2 fs error
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Fri, 3 Dec 1999 14:38:25 -0200
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>, Marc Esipovich <marc@mucom.co.il>, e1097757@ceng.metu.edu.tr, linux@cthulhu.engr.sgi.com
In-reply-to: <000c01bf3da2$dab2a400$e548e8c3@thinkpad>
References: <000c01bf3da2$dab2a400$e548e8c3@thinkpad>
Sender: owner-linuxmips@oss.sgi.com
On Fri, Dec 03, 1999 at 04:26:42PM +0100, Kevin D. Kissell wrote:

> >I've seen this happening on my Indy as well like once every month or even
> >more rarely.  It only happens very rarely but it happens.  I think the
> >hardware of my Indy is fine as all my attempts to reduce the problems I'm
> >experiencing during my development to a hardware problem have failed.

> By any chance are you guys seeing this on R5000 Indys?

Yes.

> There is an assumption in arch/mips/mm/r4xx0.c that flushing the secondary
> cache automagically flushes the same address in the primary data cache,
> but that assumption is not universally valid and there is no reason to
> believe that it is true on the R5K.

We make this assumption for R[04]00[SM]C CPUs only.  For R5000SC CPU modules
as in the Indy the assumption is that we don't need to flush the l2 caches
unless we do a DMA operation in which case the special r4k_dma_*
functions will take care of the whatever might be necessary to keep caches
consistent with DMA.

  Ralf

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