On Fri, May 28, 1999 at 01:19:45PM +0400, Vladimir A. Roganov wrote:
> We implemented it by very interesting reason: old Baget uses special
> VIC register which exists on bus only (!!!) when interrupt is active.
> But interrupt can be deactivated by external reason. In such case
> IRQ handler catch SIGBUS, what crashes current process.
> It was overwritten twice, and it looks debugged hardly :-)
> May be it can help here.
> > The other bug is that memory accesses via ptrace for virtual addresses
> > which are uncached would be executed cached, trouble ahead.
> YES, we obtained such effect.
> To avoid it we just moved to physical address space (high bits are ignored),
> but it is not good in general.
> > Further complexity is added by handling write buffers for the R3000 and
> > virtual coherency for R4000.
> Yes, it should be tried to be fixed once for every arch.
That means we need something like read_phys() and write_phys() for all
CPU variants, even board variations. The functions needs to get passed
an virtual address as well such that it can deal with virtual coherency
Then again R10k does this in hardware, so why bother ;-)