Bug

[Ulf Carlsson <grim@zigzegv.ml.org>]

Hi,

I think you forgot a break in the middle of a switch statement, setting
order to 3 is pretty nonsense otherwise.
I compiled a new kernel with my patch, and I couldn't see any changes. The
VCED is probably handled correctly by the interrupt anyway.

patch applies to arch/mips/mm/init.c

--- init.c.org  Fri Sep  4 20:34:11 1998
+++ init.c      Fri Sep  4 20:45:40 1998
@@ -126,6 +126,7 @@
        case CPU_R4400SC:
        case CPU_R4400MC:
                order = 3;
+               break;
        default:
                order = 0;
        }

- Ulf