On Tue, Aug 18, 1998 at 07:31:05PM -0700, William J. Earl wrote:
> email@example.com writes:
> > The bad thing with a bus error is that it may be delayed for a very long
> > time thus resulting in a useless program counter. What happens is that
> > the CPU writes to some invalid address but the write access over the
> > system bus is delayed because the writeback cache policy is being used.
> > Later, maybe even much later, when the cacheline gets written back to
> > memory for some reason the system board signals a bus error interrupt.
> > At this point the program counter may already be completly useless.
> You cannot get a delayed bus error on a cached write, unless
> you do a "create dirty exclusive" cache operation to validate the line
> before writing.
Linux uses Create_Dirty_Excl_D as optimization where possible, so the
probability for this to happen is relativly high. Linux however should
never use Create_Dirty_Excl_D or Create_Dirty_Excl_SD on R400SC
CPUs, have to verify this.
> You can get delayed bus errors on uncached writes,
> as to device control registers. Since any K1SEG address is uncached,
> it is not too hard to generate a bus error with a bad pointer value.