linux-mips
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Re: bus error IRQ

To: ralf@uni-koblenz.de
Subject: Re: bus error IRQ
From: "William J. Earl" <wje@fir.engr.sgi.com>
Date: Tue, 18 Aug 1998 19:31:05 -0700
Cc: Ulf Carlsson <grim@zigzegv.ml.org>, linux@cthulhu.engr.sgi.com
In-reply-to: <19980818021316.J3345@uni-koblenz.de>
References: <199808171845.UAA29545@calypso.saturn> <19980818021316.J3345@uni-koblenz.de>
Sender: owner-linux@cthulhu.engr.sgi.com
ralf@uni-koblenz.de writes:
...
 > The bad thing with a bus error is that it may be delayed for a very long
 > time thus resulting in a useless program counter.  What happens is that
 > the CPU writes to some invalid address but the write access over the
 > system bus is delayed because the writeback cache policy is being used.
 > Later, maybe even much later, when the cacheline gets written back to
 > memory for some reason the system board signals a bus error interrupt.
 > At this point the program counter may already be completly useless.
...

     You cannot get a delayed bus error on a cached write, unless
you do a "create dirty exclusive" cache operation to validate the line
before writing.  You can get delayed bus errors on uncached writes,
as to device control registers.  Since any K1SEG address is uncached,
it is not too hard to generate a bus error with a bad pointer value.

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