On Thu, May 07, 1998 at 09:09:46AM -0700, David S. Miller wrote:
> Ralf did you fix GLIBC to init the FPU csr correctly? It should be
> set to zero, and the code we had originally did not do this, it set it
> to a bunch of values which induced traps for operations where they
> shouldn't by default. I fixed this in the Cobalt glibc tree a long
> time ago and we have no FPU emulator code in the kernel.
I've just taken a look at the sources and found that the various
architectures seem to handle this issue differently by default.
Sparc disables the exceptions, Intel enables all IEEE754 exceptions,
MIPS only division by zero and overflow and Alpha handles things a bit
different anyway ...
Seems there still is no common dominator on what should be default and
I don't think either 0x00000600 or 0x0 is clearly right or wrong.
Ok, without the kernel fp stuff zero is somewhat better, so I'm going
to use it. From the kernel side new born processes default to $fcr31=0
already. Whatever, this smells like making a kludge just a little bit