On Mon, Dec 22, 1997 at 01:15:59AM -0800, Mike Shaver wrote:
> OK, I've been tracking a bug that only seems to appear on the Indy I
> have at home right now (belongs to the housemates). After sgiseeq_init
> allocates the ring buffers, it calls flush_cache_all(). On this system,
> that zeroes out the ring buffer pointers (rx and tx -- likely the entire
> dev->priv block and more) and then setup_tx_ring gets understandably
> upset. =)
>
> Anyway, I'm not enough of a MIPS guru to really say much more, but I'll
> poke around tonight and see if I can stumble across anything useful.
>
> Linux reports:
> MIPS 4400 FPU<MIPS-R4400FPC> ICACHE DCACHE SCACHE
There is a bug in the l2 flushing for theSC/MC versions, it uses the
wrong cacheops. I've fixed it in my home tree.
Ralf
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