OK, I've been tracking a bug that only seems to appear on the Indy I
have at home right now (belongs to the housemates). After sgiseeq_init
allocates the ring buffers, it calls flush_cache_all(). On this system,
that zeroes out the ring buffer pointers (rx and tx -- likely the entire
dev->priv block and more) and then setup_tx_ring gets understandably
upset. =)
Anyway, I'm not enough of a MIPS guru to really say much more, but I'll
poke around tonight and see if I can stumble across anything useful.
Linux reports:
MIPS 4400 FPU<MIPS-R4400FPC> ICACHE DCACHE SCACHE
CPU Revision 0460
hinv tells me:
1 200 MHZ IP22 Processor
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
CPU: MIPS R4400 Processor Chip Revision: 6.0
Instruction cache size: 16 Kbytes
Data cache size: 16 Kbytes
More than this I do not know, but I'll run any test that doesn't risk
permanent damage.
Mike
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