On Thu, Dec 11, 1997 at 07:15:22PM -0800, William J. Earl wrote:
> email@example.com writes:
> > William: would an attempt to manipulate the R4600 second level cache on
> > a Indy without such a cache result in a bus error interrupt?
> Yes. The memory address of the cache controller will not exist. Avoid
> referencing it when the cache is not configured. If the kernel is not
> reading the cache configuration from the CPU module EEPROM, then it should
> test for the existence of the cache controller by referencing it within
> some sort of exception trap which returns control gracefully with an error
> indication if a bus error occurs. Note that you might get a bus error
> (on a read) rather than a bus error interrupt (on a write).
Ok, this prooves that my theories have been correct. In fact the Indy
code tries to be intelligent about recognicing a second level cache but
fails to get things right when flushing the cache. Assume this bug to
be fixed for the next release.
There seems to be something else wrong with the cache handling. My R5000
Indy has a second level cache according to hinv but it doesn't show up
in the results of lmbench running under Linux.
Indeed, we only activate the second level cache for R4600 machines. I
guess the next kernel release will be *faster* :-)