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Re: Magnum 4000 caches

To: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
Subject: Re: Magnum 4000 caches
From: "William J. Earl" <wje@fir.engr.sgi.com>
Date: Thu, 23 Oct 1997 11:47:43 -0700
Cc: linux@cthulhu.engr.sgi.com
In-reply-to: <199710231825.UAA26628@informatik.uni-koblenz.de>
References: <199710231808.LAA11992@fir.engr.sgi.com> <199710231825.UAA26628@informatik.uni-koblenz.de>
Sender: owner-linux@cthulhu.engr.sgi.com
Ralf Baechle writes:
...
 > >        The R6000 is a real challenge.  It is substantially different
 > > from the R3000 and R4000.  In particular, it uses part of the cache
 > > as a sort of second level TLB.  ES/IX is the CDC version of MP RISC/os.
 > > (MIPS worked on MP RISC/os, but never shipped it to customers; CDC took
 > > it over as a product.)  The I/O is fairly straightforward, being mostly
 > > VME devices, but it does include I/O address mapping hardware which must
 > > be configured.
 > 
 > Is the information in newer releases of Kane's MIPS bible sufficient to
 > do the R6000 part of the job?  I guess the company (BIT ???) that made the
 > R6000 is no longer around, so it would make sense if Roman'd ask them
 > for a manual ...

     BIT made the parts originally, but we later got the parts from NEC.
The latter were faster, more reliable, and much cheaper.  CDC might still
provide the manuals.  As far as I know, the R6000 is not well documented
in the regular MIPS documentation.  I might, however, be able to get you
some information about processor issues.


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