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Re: Magnum 4000 caches

To: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
Subject: Re: Magnum 4000 caches
From: "William J. Earl" <wje@fir.engr.sgi.com>
Date: Thu, 23 Oct 1997 10:21:41 -0700
Cc: linux@cthulhu.engr.sgi.com
In-reply-to: <199710231706.TAA24158@informatik.uni-koblenz.de>
References: <199710231706.TAA24158@informatik.uni-koblenz.de>
Sender: owner-linux@cthulhu.engr.sgi.com
Ralf Baechle writes:
 > Hi,
 > 
 > maybe one of the old Mips people can answer me two questions:
 > 
 >  - why do the Magnum 4000PC instruction and data caches have a different
 >    linesize for the L1 caches, but the Magnum 4000SC not?

     It turned out that, at least for some workloads, the 4000PC
worked better that way.  (If I remember correctly, a 32-byte linesize
is better for the icache, since a 4-instruction basic block is
unusual.)  However, not all boxes use the same linesize values,
because there were hardware bugs with at least some of the memory
controllers which were affected by the choice of linesize.  I don't
remember the details anymore, although I might find them in my mail
archivies.  I have a 4000PC system (32-byte I, 16-byte D, MCT version 3)
and two 4000SC systems (16-byte I, D, and S, MCT version 2) still online.
I think that MCT version 2 would not support a 32-byte line.
 
 >  - does the Magnum 4000SC use a split instruction/data L2 cache?

     No, it has a unified writeback L2 cache.

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